Rocketio Transceiver Instantiations; Hdl Code Examples; Pll Operation And Clock Recovery; Clock Correction Count - Xilinx RocketIO User Manual

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RocketIO Transceiver Instantiations

For the different clocking schemes, several things must change, including the clock
frequency for USRCLK and USRCLK2 discussed in the DCM section above. The data and
control ports for GT_CUSTOM must also reflect this change in data width by
concatenating zeros onto inputs and wires for outputs for Verilog designs, and by setting
outputs to open and concatenating zeros on unused input bits for VHDL designs.

HDL Code Examples

For code examples, see the Virtex-II Pro Platform FPGA Handbook web page at:
http://www.xilinx.com/publications/products/v2pro/handbook/index.htm

PLL Operation and Clock Recovery

The clock correction sequence is a special sequence to accommodate frequency differences
between the received data (as reflected in RXRECCLK) and RXUSRCLK. Most of the
primitives have these defaulted to the respective protocols. Only the GT_CUSTOM allows
this sequence to be set to any specific protocol. The sequence contains 11 bits including the
10 bits of serial data. The 11th bit has two different formats. The typical usage is:
Table 3-10
value, and the parallel data interface, and how each corresponds with the other.

Table 3-10: Clock Correction Sequence / Data Correlation for 16-Bit Data Port

The GT_CUSTOM transceiver examples use the previous sequence for clock correction.

Clock Correction Count

The clock correction count signal (RXCLKCORCNT) is a three-bit signal. It signals if the
clock correction has occurred and whether the elastic buffer realigned the data by skipping
or repeating data in the buffer. It also signals if channel bonding has occurred

Table 3-11: RXCLKCORCNT Definition

56
0, disparity error required, char is K, 8-bit data value (after
8B/10B decoding)
1, 10 bit data value (without 8B/10B decoding)
is an example of data 11-bit attribute setting, the character value, CHARISK
Attribute Setting
CLK_COR_SEQ_1_1 = 00110111100
CLK_COR_SEQ_1_2 = 00010010101
CLK_COR_SEQ_1_3 = 00010110101
CLK_COR_SEQ_1_4 = 00010110101
RXCLKCORCNT[2:0]
000
001
010
011
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Chapter 3: Digital Design Considerations
Character
K28.5
D21.4
D21.5
D21.5
Significance
No channel bonding or clock correction occurred for current
RXDATA
Elastic buffer skipped one clock correction sequence for
current RXDATA
Elastic buffer skipped two clock correction sequence for
current RXDATA
Elastic buffer skipped three clock correction sequence for
current RXDATA
CHARISK TXDATA (hex)
1
0
0
0
(Table
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
BC
95
B5
B5
3-11).