Multiplexed Clocking Scheme; Data Path Latency; Transmitter Latency; Figure 3-8: Multiplexed Refclk - Xilinx RocketIO User Manual

Clocking

Multiplexed Clocking Scheme

Following configuration of the FPGA, some applications might need to change the
frequency of its REFCLK depending on the protocol used.
design can use two different reference clocks connected to two different DCMs. The clocks
are then multiplexed before input into the RocketIO transceiver.
User logic can be designed to determine during autonegotiation if the reference clock used
for the transceiver is incorrect. If so, the transceiver must then be reset and another
reference clock selected.

Data Path Latency

With the many configurations of the MGT, both the transmit and receive latency of the data
path varies. Below are several tables that provide approximate latencies for common
configurations.

Transmitter Latency

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•
•
•
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
IBUFG
REFCLK
REFCLK2
REFCLKSEL
Latencies for
- TX_BUFFER_USE = TRUE
- TX_CRC_USE = FALSE
- SERDES_10B = FALSE
TX_DATA_WIDTH
(Approx. TXUSRCLK Cycles)
1
2
4
If TX FIFO bypassed (TX_BUFFER_USE = FALSE), subtract 4
If TX CRC is used (TX_CRC_USE = TRUE), add 6
For half-rate option (SERDES_10B = TRUE). subtract 1 (approx.)
www.xilinx.com
1-800-255-7778
DCM
CLKIN
CLKFB
RST
CLK0
DCM
CLKIN
0
CLKFB
RST
CLK0 1
BUFGMUX

Figure 3-8: Multiplexed REFCLK

Latency
8.75
8.5
10
Figure 3-8 shows how the
GT_std_2
REFCLK
REFCLK2
REFCLKSEL
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
Use of 2 DCMs is required
to maintain correct
IBUFG/DCM/BUFGMUX topology
for clock skew compensation
UG024_05_020802
R
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