Chapter 8: Low-Latency Design; Introduction - Xilinx Virtex-4 RocketIO User Manual

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Low-Latency Design

Introduction

The Virtex®-4 RocketIO™ Multi-Gigabyte Transceiver (MGT) has the flexibility to
minimize latency in the PCS.
The RocketIO transceiver contains two buffers, one for the transmitter and one for the
receiver. The RX buffer is a ring buffer that supports clock correction and channel bonding.
Specifically, these buffers allow for phase differences between PCS RXCLK and
RXUSRCLK, as shown in
Figure
Some applications do not require the full feature set of the PCS, and a user can choose to
minimize latency from/to the serial pins (RXP/RXN, TXP/TXN). For these applications,
the MGT includes parallel clock synchronization features that align the PMA-generated
parallel clock (PMA XCLK0) to a parallel clock sourced from the PCS (PCS XCLK), making
it possible to bypass the RX buffer and TX buffer. The transmitter and receiver data paths
include PCS bypass muxes that allow PCS features to be bypassed in these clocking modes.
Refer to
RXDATA_SEL and TXDATA_SEL attributes respectively.
For the RX, latency reduction is achieved by using the RX Buffer (RX Low Latency Buffered
Mode) or by bypassing the RX Buffer (RX Low Latency Buffer Bypass Mode). The latter
mode supports the low-latency data path bypass options selected via RXDATA_SEL:
•
•
•
•
For the TX, latency reduction is achieved by bypassing features of the PCS (TX Low
Latency Buffered Mode) or by bypassing the TX Buffer and/or PCS features (TX Low
Latency Buffer Bypass Mode). These reduced-latency bypass options are selected via
TXDATA_SEL:
•
•
•
Virtex-4 RocketIO MGT User Guide
UG076 (v4.1) November 2, 2008
Figure
8-2.
Figure 8-1 and Figure 8-2
RXDATA_SEL = 00 — full data path
RXDATA_SEL = 01 — data directly from PMA interface
RXDATA_SEL = 10 — data directly from alignment block
RXDATA_SEL = 11 — data directly from 8B/10B decoder
TXDATA_SEL = 00 — full data path
TXDATA_SEL = 01 — data directly from fabric interface
TXDATA_SEL = 10 — data directly from output of 8B/10B encoder
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8-1, or between PCS TXCLK and TXUSRCLK, as shown in
for the buffer bypass muxing options selected by the
Chapter 8
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