Timing Of On-Chip Supporting Modules - Renesas H8S/2633 Series Hardware Manual

27.3.4

Timing of On-Chip Supporting Modules

Table 27-7 lists the timing of on-chip supporting modules.
Table 27-7 Timing of On-Chip Supporting Modules
Condition: PV = 4.5 V to 5.5 V, AV
CC
V = AV
SS
specifications), T
Item
I/O port Output data delay time
Input data setup time
Input data hold time
TPU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock Single edge
pulse width Both edges
WDT0 Overflow output delay time
SCI Input clock Asynchronous
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time
Receive data setup time
(synchronous)
Receive data hold time
(synchronous)
A/D Trigger input setup time
converter
CC
= PLLV = 0 V, ø = 2 to 28 MHz, T
SS SS
= –40°C to +85°C (wide-range specifications)
a
Symbol
t
PWD
t
PRS
t
PRH
t
TOCD
t
TICS
t
TCKS
t
TCKWH
t
TCKWL
t
WOVD
t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
= 4.5 V to 5.5 V, V
ref
= –20°C to +75°C (regular
a
Min Max
— 40
25 —
25 —
— 40
25 —
25 —
1.5 —
2.5 —
— 40
4 —
6 —
0.4 0.6
— 1.5
— 1.5
— 40
40 —
40 —
40 —
= 4.5 V to AV ,
CC
Unit Test Conditions
ns Figure 27-13
ns Figure 27-14
ns Figure 27-15
t
cyc
ns Figure 27-16
t Figure 27-17
cyc
t
Scyc
t
cyc
ns Figure 27-18
ns Figure 27-19
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