Clock Timing - Renesas H8S/2633 Series Hardware Manual

27.3.1

Clock Timing

Table 27-4 lists the clock timing
Table 27-4 Clock Timing
Condition: PV = 4.5 V to 5.5 V, AV
CC
V = AV
SS
T = –40°C to +85°C (wide-range specifications)
a
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator settling
time at reset (crystal)
Clock oscillator settling time in
software standby (crystal)
External clock output stabilization
delay time
Note: * The input clock frequency should be set to 25 MHz or less. If ø = 25 MHz to 28 MHz, use
the PLL to multiply the frequency (×2 or ×4).
1092
= 4.5 V to 5.5 V, V
CC
= 0 V, ø = 2 to 28 MHz * , T
SS
Symbol
t
cyc
t
CH
t
CL
t
Cr
t
Cf
t
OSC1
t
OSC2
t
DEXT
= 4.5 V to AV
ref
= –20°C to +75°C (regular specifications),
a
28MHz
Min Max Unit
35.7 500 ns
10 — ns
10 — ns
— 5 ns
— 5 ns
10 — ms
5 — ms
2 — ms
,
CC
Test Conditions
Figure 27-2
Figure 27-3
Figure 24-3
Figure 27-3