Timing Of On-Chip Supporting Modules - Renesas H8S/2633 Series Hardware Manual

26.3.5

Timing of On-Chip Supporting Modules

Table 26-9 lists the timing of on-chip supporting modules.
Table 26-9 Timing of On-Chip Supporting Modules
Condition: PV = 4.5 V to 5.5 V, AV
CC
V = AV
SS
T = –20°C to +75°C (regular specifications), T
a
specifications)
Item
I/O port Output data delay time
Input data setup time
Input data hold time
PPG Pulse output delay time
TPU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock Single edge
pulse width Both edges
TMR Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock Single edge
pulse width Both edges
WDT0 Overflow output delay time
WDT1 Buzz output delay time
PWM Pulse output delay time
SCI Input clock Asynchronous
cycle
Input clock pulse width
Input clock rise time
Input clock fall time
CC
= PLLV = 0 V, ø = 32.768 kHz*, 2 to 28 MHz,
SS SS
Symbol
t
PWD
t
PRS
t
PRH
t
POD
t
TOCD
t
TICS
t
TCKS
t
TCKWH
t
TCKWL
t
TMOD
t
TMRS
t
TMCS
t
TMCWH
t
TMCWL
t
WOVD
t
BUZD
t
PWOD
t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
= 4.5 V to 5.5 V, V
ref
= –40°C to +85°C (wide-range
a
Min Max
— 40
25 —
25 —
— 40
— 40
25 —
25 —
1.5 —
2.5 —
— 40
25 —
25 —
1.5 —
2.5 —
— 40
— 40
— 40
4 —
6 —
0.4 0.6
— 1.5
— 1.5
= 4.5 V to AV ,
CC
Unit Test Conditions
ns Figure 26-20
ns Figure 26-21
ns Figure 26-22
ns Figure 26-23
t
cyc
ns Figure 26-24
ns Figure 26-26
ns Figure 26-25
t
cyc
ns Figure 26-27
ns Figure 26-28
ns Figure 26-29
t Figure 26-30
cyc
t
Scyc
t
cyc
1075