Bus Reset Output Puns - Renesas PFESiP/V850EP1 User Manual

1.7.7 Bus reset output puns

(1) External Memory interface pins
The access timing of the external bus reset output pun is described below.
Parameter
VBRESTOZ output delay time (from VBCLKOUT ↓ )
VBCLKOUT
(output)
VBRESTOZ
(output)
(2) SiP internal-connection bus interface pins
The access timing of the SiP internal-connection bus reset output pin is described below.
Parameter
SRESTOZ output delay time (from VBCLKOUT ↓ )
VBCLKOUT
(output)
SRESTOZ
(output)
CHAPTER 1 PRODUCT SPECIFCATIONS
Table 1-19. External Bus Reset Output Pin
t
DVBRESZ
Figure 1-22. External Bus Reset Output Pin
< t >
DVBRESZ
Table 1-20. SiP Internal-connection Bus Interface Pin
t
DVBRESZ
Figure 1-23. SiP Internal-connection Bus Reset Output Pin
< t >
DVBRESZ
User's Manual A19069EJ2V0UM
Symbol MIN.
1.0
Symbol MIN.
1.0
MAX. Unit
10.0 ns
MAX. Unit
8.0 ns
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