Receive Overrun Register (Rovrr); Reception Interrupt Enable Register (Rier) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

23.6.16 Receive Overrun Register (ROVRR)

If the reception completion register (RCR) is already 1 when storing of the received message in the message
buffer (x) is completed, ROVRx is set to 1, meaning that reception overruns.
n Receive overrun register (ROVRR)
Address: 00004D (CAN0)
H
Address: 00007D (CAN1)
H
Read/write →
Initial value →
Address: 00004C (CAN0)
H
Address: 00007C (CAN1)
H
Read/write →
Initial value →
When 0 is written to ROVRx, ROVRx is set to 0. When 1 is written to ROVRx, the write is ignored. When 0
is written to ROVRx after making sure that the reception overruns, ROVRx is set to 0.
1 is read when a read-modify-write instruction is performed.
Note: If setting to 1 and clearing by writing 0 occur at the same time, the bit is set to 1.

23.6.17 Reception Interrupt Enable Register (RIER)

Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer
(x).
The reception interrupt is generated at reception completion (when RCx of the reception complete register
(RCR) is 1).
n Reception interrupt enable register (RIER)
Address: 00004F (CAN0)
H
Address: 00007F (CAN1)
H
Read/write →
Initial value →
Address: 00004E (CAN0)
H
Address: 00007E (CAN1)
H
Read/write →
Initial value →
0: Reception interrupt disabled
1: Reception interrupt enabled
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
15 14 13
ROVR15 ROVR14 ROVR13
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
ROVR7 ROVR6 ROVR5
(R/W) (R/W) (R/W)
(0) (0) (0)
15 14 13
RIE15 RIE14 RIE13
(R/W) (R/W) (R/W)
(0) (0) (0)
7 6 5
RIE7 RIE6 RIE5
(R/W) (R/W) (R/W)
(0) (0) (0)
23-24
12 11 10
ROVR12 ROVR11 ROVR10
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
ROVR4 ROVR3 ROVR2
(R/W) (R/W) (R/W)
(0) (0) (0)
12 11 10
RIE12 RIE11 RIE10
(R/W) (R/W) (R/W)
(0) (0) (0)
4 3 2
RIE4 RTIE3 RIE2
(R/W) (R/W) (R/W)
(0) (0) (0)
← Bit No.
9 8
ROVR9 ROVR8
(R/W) (R/W)
(0) (0)
← Bit No.
1 0
ROVR1 ROVR0
(R/W) (R/W)
(0) (0)
← Bit No.
9 8
RIE9 RIE8
(R/W) (R/W)
(0) (0)
← Bit No.
1 0
RIE1 RIE0
(R/W) (R/W)
(0) (0)