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CHAPTER 1 OVERVIEW OF MB90480/485 SERIES
1.2
Block Diagram of MB90480/485 Series
This section has a block diagram of the MB90480/485 series.
■
Block diagram of MB90480/485 series
Figure 1.2-1 is a block diagram of the MB90480/485 series.
P00 to P07 (8 pins) : with an input pull-up resistance setting register.
P10 to P17 (8 pins) : with an input pull-up resistance setting register.
P40 to P47 (8 pins) : with an open drain setting register.
P70 to P75 (6 pins) : with an open drain setting register.
MB90485 series only
• I
2
C pin P77 and P76 are N-ch open drain pin (without P-ch) . However, MB90V485B uses the N-ch open drain pin (with P-ch) .
• P20 to P27, P30 to P37, P40 to P47 and P70 to P77 also used as 3 V/5 V I/F pin.
• As for MB90V485B, input pins (PWC0, PWC1, PWC2/EXTC/SCL and SDA pins) for PWC/μPG/I
Note:
In the Figure 1.2-1, the I/O port shares a pin with each built-in function block. The pin cannot be
used as an I/O port if it is used as a built-in module pin.
6
Figure 1.2-1 Block diagram of MB90480/485 Series
X0, X1, RST
Clock control
X0A, X1A
8
circuit
MD2, MD1, MD0
RAM
ROM
μDMAC
Communication
prescaler
2
SIN0
UART
SOT0
SCK0
SIN1, SIN2
I/O extended serial
SOT1, SOT 2
interface × 2 channels
SCK1, SCK2
AV
CC
AVRH
A/D converter
AV
SS
( 10-bit )
ADTG
to
AN0
AN7
PWC0
PWC × 3 channels
PWC1
PWC2
8
8
8
P00
P10
P20
to
to
to
P07
P17
P27
: Only for MB90485 series
CPU
2
F
MC16LX core
Interrupt controller
8/16-bit PPG
8/16-bit
up/down counter
μPG
Chip select
Input/output timer
16-bit input capture ×
2 channels
16-bit output compare
×
2 channels
16-bit reload timer
2
I
C interface
External interrupt
I/O port
8
8
8
8
8
8
8
4
P30
P40
P50
P60
P70
P80
P90
PA0
to
to
to
to
to
to
to
to
P37
P47
P57
P67
P77
P87
P97
PA3
PPG0, PPG1
PPG2, PPG3
PPG4, PPG5
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
EXTC
MT00
MT01
CS0, CS1,
CS2, CS3
IN0, IN1
OUT0, OUT1,
OUT2, OUT3,
OUT4, OUT5
TIN0
TOT0
SCL
SDA
8
to
IRQ0
IRQ7
2
C become CMOS input.
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