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(7) Operation description
A-D conversion is started with the A-D conversion start instruction
(ADST). The internal operation during A-D conversion is as follows:
When A-D conversion starts, the register AD is cleared to
"000
."
16
Next, the topmost bit of the register AD is set to "1," and the
comparison voltage V
is compared with the analog input volt-
ref
age V
.
IN
When the comparison result is V
register AD remains set to "1." When the comparison result is
V
> V
, it is cleared to "0."
ref
IN
Table 16 Change of successive comparison register AD during A-D conversion
At starting conversion
1st comparison
2nd comparison
3rd comparison
After 10th comparison
completes
1: 1st comparison result
3: 3rd comparison result
9: 9th comparison result
< V
, the topmost bit of the
ref
IN
Change of successive comparison register AD
-------------
-----
1
0
0
-------------
-------------
-----
1
1
0
-------------
-------------
-----
1
2
1
-------------
A-D conversion result
-------------
-----
1
2
3
-------------
2: 2nd comparison result
8: 8th comparison result
A: 10th comparison result
4513/4514 Group User's Manual
FUNCTION BLOCK OPERATIONS
The 4513/4514 Group repeats this operation to the lowermost bit of
the register AD to convert an analog value to a digital value. A-D
conversion stops after 62 machine cycles (46.5 s when f(X
4.0 MHz in high-speed mode) from the start, and the conversion re-
sult is stored in the register AD. An A-D interrupt activated condition
is satisfied and the ADF flag is set to "1" as soon as A-D conversion
completes (Figure 27).
V
DD
0
0
0
2
V
DD
0
0
0
2
V
DD
0
0
0
2
V
DD
8
9
A
2
HARDWARE
Comparison voltage (V
) value
ref
V
DD
±
4
V
V
DD
DD
±
±
4
8
V
DD
±
±
1024
) =
IN
1-43
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