Receive Shift Register (Frsr); Receive Buffer Register (Frbr) - Renesas H8S/2100 Series Hardware Manual

Table 17.3 Register Access
SCIFE Bit in HICR5
Bit 3 in MSTPCRB
SCIFCR
Other than SCIFCR
Notes: 1. When LPC access is set, writing from the H8S CPU is disabled. The read value is H'FF.
2. When H8S CPU access is set, writing from the LPC is disabled. The read value is H'00.
17.3.1

Receive Shift Register (FRSR)

FRSR is a register that receives data and converts serial data input from the FRxD pin to parallel
data. It stores the data in the order received from the LSB (bit 0). When one frame of serial data
has been received, the data is transferred to FRBR.
FRSR cannot be read from the CPU/LPC interface.
17.3.2

Receive Buffer Register (FRBR)

FRBR is an 8-bit read-only register that stores received serial data. It can read data correctly when
the DR bit in FLSR is set.
When the FIFO is disabled, the data in FRBR must be read before the next data is received. If new
data is received before the remaining data is read, the data is overwritten, resulting in an overrun
error.
When this register is read with the FIFO enabled, the first buffer of the receive FIFO is read.
When the receive FIFO becomes full, the subsequent receive data is lost, resulting in an overrun
error.
Bit Bit Name
7 to 0 Bit 7 to
bit 0
0
0
H8S CPU
2
access*
H8S CPU
2
access*
Initial Value R/W
All 0 R
Section 17 Serial Communication Interface with FIFO (SCIF)
1 0
Access disabled H8S CPU
access*
Access disabled LPC access*
Description
Stores received serial data.
The data is 16 bytes when the FIFO is enabled.
Rev. 1.00 Apr. 28, 2008 Page 497 of 994
1
1
Access disabled
2
1
LPC access*
REJ09B0452-0100
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