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1.2
Block Diagram
Figure 1.1 shows an internal block diagram of the SH7750.
CCN:
Cache and TLB controller
BSC:
Bus state controller
CPG:
Clock pulse generator
DMAC: Direct memory access controller
FPU:
Floating-point unit
INTC:
Interrupt controller
ITLB:
Instruction TLB (translation lookaside buffer)
Rev. 2.0, 03/99, page 8 of 396
CPU
I cache
(8 kB)
CPG
INTC
SCI
(SCIF)
RTC
TMU
Figure 1.1 Block Diagram of SH7750 Functions
UBC
Lower 32-bit data
Lower 32-bit data
ITLB
CCN
UTLB
BSC
External
bus interface
26-bit
64-bit
address
data
UTLB: Unified TLB (translation lookaside buffer)
RTC:
Realtime clock
SCI:
Serial communication interface
SCIF:
Serial communication interface with FIFO
TMU:
Timer unit
UBC:
User break controller
FPU
O cache
(16 kB)
DMAC
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