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Chapter 8
System Interface Operation
This chapter describes the MPC750 microprocessor bus interface and its operation.
It
shows how the MPC750 signals, defined in Chapter 7, "Signal Descriptions," interact to
perform address and data transfers.
8.1 MPC750 System Interface Overview
The system interface prioritizes requests for bus operations from the instruction and data
caches, and performs bus operations in accordance with the protocol described in the
PowerPC Microprocessor Family: The Bus Interface for 32-Bit Microprocessors. It
includes address register queues, prioritization logic, and bus control unit. The system
interface latches snoop addresses for snooping in the data cache and in the address register
queues, and for reservations controlled by the Load Word and Reserve Indexed (lwarx) and
Store Word Conditional Indexed (stwcx.) instructions, and maintains the touch load address
for the cache. The interface allows one level of pipelining; that is, with certain restrictions
discussed later, there can be two outstanding transactions at any given time. Accesses are
prioritized with load operations preceding store operations.
Instructions are automatically fetched from the memory system into the instruction unit
where they are dispatched to the execution units at a peak rate of two instructions per clock.
Conversely, load and store instructions explicitly specify the movement of operands to and
from the integer and floating-point register files and the memory system.
When the MPC750 encounters an instruction or data access, it calculates the logical address
(effective address in the architecture specification) and uses the low-order address bits to
check for a hit in the on-chip, 32-Kbyte instruction and data caches. During cache lookup,
the instruction and data memory management units (MMUs) use the higher-order address
bits to calculate the virtual address, from which they calculate the physical address (real
address in the architecture specification). The physical address bits are then compared with
the corresponding cache tag bits to determine if a cache hit occurred in the Ll instruction
or data cache. If the access misses in the corresponding cache, the physical address is used
to access the L2 cache tags (if the L2 cache is enabled). If no match is found in the L2 cache
tags, the physical address is used to access system memory.
In addition to the loads, stores, and instruction fetches, the MPC750 performs hardware
table search operations following TLB misses, L2 cache cast-out operations when
Chapter 8. System Interface Operation
8-1
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