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¥ Timing of GPL[0Ð5]ÑIn the MPC8xxÕs UPM, the GPL lines could change on the
positive edge of T2 or T3. In the MPC8260 these signals can change in the positive
edge of T1 or T3 to allow connection to high-speed synchronous devices such as
burst SRAM.
¥ UPM controlled signals negated at end of an accessÑIn the MPC8xxÕs UPM, if the
user did not negate the UPM signals at end of an access, those signals kept their
previous value. In the PowerQUICC II, all UPM signals are negated
(CS,BS,GPL[0:4] driven to logic 1 and GPL5 driven to logic 0) at the end of that
cycle, unless there is a back-to-back UPM cycle pending. In many cases this allows
the UPM routine to Þnish one cycle earlier because it is now possible and desired to
assert both UTA and LAST.
¥ MCR is eliminatedÑIn the MPC8260, MCR is eliminated. The function of RAM
read/write and RUN is done via the MxMR.
¥ UTA polarity is reversedÑIn the MPC8260, UTA is active-high.
¥ The disable timer control (TODT) and LAST bit in the RAM array word must be set
together, otherwise TODT is ignored.
¥ Refresh timer value is in a separate registerÑIn the MPC8260, the refresh timer
value has moved to two registers, PURT and LURT, which can serve multiple UPMs.
¥ Refresh on the 60x bus must be done in UPMA; on the local bus, it must be done in
UPMB.
¥ New feature: Repeated execution of the current RAM word (REDO).
¥ Extended hold time on reads can be up to 8 clock cycles instead of 1 in the MPC8xx.
10.7 Memory System Interface Example Using UPM
onnecting the MPC8260 to a DRAM device requires a detailed examination of the timing
C
diagrams representing the possible memory cycles that must be performed when accessing
this device. This section provides timing diagrams for various UPM conÞgurations.
MOTOROLA
Chapter 10. Memory Controller
Part III. The Hardware Interface
10-81
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