AGFA Avantra 36/44 Service Manual page 94

3.2.3.9 OCP Register Test
To test the OCP register, a two byte pattern is written into it. The first byte is the
real data, and the second byte is used to retrieve the feedback.
3.2.3.10 FLASHROM Cheksum
The flash memory stores the 2400 and 3600 dpi correction table entries and DSP
code. As the boot diagnostics progress, they display a checksum of both the 2400
and 3600 dpi correction tables for the checksum of the DSP code. The checksum
algorithm is a summation of all the flash memory locations occupied by a particular
table or DSP code.
3.2.3.11 Correction SRAM Test
The correction SRAM test performs a read/write test of the SRAM to verify its integ-
rity. The correction SRAM addressing is done via the offgate register.
First, the starting address value loads into the offgate register. Second, the auto-
increment mode is selected, and a pattern is written into the SRAM. Each write in
auto-increment mode increments the address pointer. After the SRAM has been
written, the offgate register reloads with the same starting address. The contents of
the SRAM are read back and compared against the expected data pattern. Dispari-
ties are reported as an error.
3.2.3.12 Correction State Machine
The correction state machine provides event synchronization based on the phase
lock loop derived from the spinner motor or a fake clock. Correction values store
in flash memory and load into the correction SRAM prior to running the correction
state machine. This test checks correct operation of the correction state machine by
monitoring the signal at the event PAL. There should be a 5.3 KHZ pulse at the
event PAL if the correction state machine is running properly.
3.2.3.13 Correction SRAM Checksum Test
After the correction SRAM load from the FLASHROM, a checksum is performed to
verify that the data loaded properly. The checksum algorithm is a summation of all
the SRAM memory locations occupied by the correction table.
Section I: Imagesetter
Diagnostics 3-7