Chip Configuration Module Block Diagram; Master Mode; Single-Chip Mode - Motorola ColdFire MCF5281 User Manual

Block Diagram

30.2.1 Master Mode

In master mode, the central processor unit (CPU) can access external memories and
peripherals. The external bus consists of a 32-bit data bus and 24 address lines. The
available bus control signals include R/W, TS, TIP, TSIZ[1:0], TA, TEA, OE, and BS[3:0].
Up to seven chip selects can be programmed to select and control external devices and to
provide bus cycle termination. When interfacing to 16-bit ports, the port C and D pins and
PJ[5:4] (BS[1:0]) can be configured as general-purpose input/output (I/O), and when
interfacing to 8-bit ports, the ports B, C and D pins and PJ[7:5] (BS[3:1]) can be configured
as general purpose input/output (I/O).

30.2.2 Single-Chip Mode

In single-chip mode, all memory is internal to the chip. All external bus pins are configured
as general purpose I/O.
30.3 Block Diagram
Reset Output Pad
Configuration Strength Selection
Chip Mode Clock Mode
Selection Selection
Boot Device / Port Chip Select
Size Selection Configuration
Chip Configuration Register
Reset Configuration Register
Chip Identification Register
Chip Test Register
Figure 30-1. Chip Configuration Module Block Diagram
30-2 MCF5282 User's Manual MOTOROLA