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Reset
Clock Mode
External clock mode; PLL disabled
1:1 PLL mode
Normal PLL mode; external clock reference
Normal PLL mode; crystal oscillator reference
1
Modifying the default configurations is possible only if the external RCON pin is asserted low.
30.6.6 Chip Select Configuration
The chip select configuration (CS[6:4]) is selected during reset and reflected in the RCSC
field of the CCR. Once reset is exited, the chip select configuration cannot be changed.
Table 30-10 shows the different chip select configurations that can be implemented during
reset configuration.
30.7 Reset
Reset initializes CCM registers to a known startup state as described in Section 30.5,
"Memory Map and Registers." The CCM controls chip configuration at reset as described
in Section 30.6, "Functional Description."
30.8 Interrupts
The CCM does not generate interrupt requests.
30-12
Table 30-13. Clock Mode Selection
PLLSEL Bit
0
0
1
1
MCF5282 User's Manual
1
Synthesizer Status Register (SYNSR)
PLLREF Bit
0
0
0
1
PLLMOD
0
1
1
1
MOTOROLA
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