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Signal Connection Considerations
Figure 27-51. Input Signal Subjected to Positive Stress
The current into the signal (I
these equations:
Where:
V
= Adjustable voltage source
Stress
V
= Parasitic PNP emitter/base voltage
EB
V
= Parasitic NPN base/emitter voltage
BE
R
= Source impedance (10 kΩ resistor in Figure 27-50 and Figure 27-51 on stressed
Stress
channel)
R
= Source impedance on channel selected for conversion
Selected
The current into (I
) the neighboring pin is determined by the K
In
of the parasitic bipolar transistor (K
I
= – K
* I
In
N
INJ
Where:
I
is either I
or I
INJ
INJN
A method for minimizing the impact of stress conditions on the QADC is to strategically
allocate QADC inputs so that the lower accuracy inputs are adjacent to the inputs most
likely to see stress conditions.
Also, suitable source impedances should be selected to meet design goals and minimize the
effect of stress conditions.
27-70
V
STRESS
R
STRESS
+
10 kΩ
R
SELECTED
V
IN
or I
) under negative or positive stress is determined by
INJN
INJP
–
I INJN
=
-------------------------------------------- -
V
I
=
-------------------------------------------------------------
INJP
‹‹ 1). The I
N
.
INJP
MCF5282 User's Manual
I
AN
Signal Under
injP
n
Stress
Parasitic
Device
I
IN
Adjacent
AN
Signal
n+1
(
)
V
–
V
Stress
BE
R Stress
–
V
–
V
Stress
EB
DDA
R
Stress
can be expressed by this equation:
In
V
DDA
(current coupling ratio)
N
MOTOROLA
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