Motorola ColdFire MCF5281 User Manual page 115

This register performs a simple AND with the operand address for MAC instructions. That
is, the processor calculates the normal operand address and, if enabled, that address is then
ANDed with {0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain
MASK bits cleared, the operand address can be constrained to a certain memory region.
This is used primarily to implement circular queues in conjunction with the (An)+
addressing mode.
This feature minimizes the addressing support required for filtering, convolution, or any
routine that implements a data array as a circular queue. For MAC + MOVE operations, the
MASK contents can optionally be included in all memory effective address calculations.
The syntax is as follows:
MAC.sz Ry,RxSF,<ea>y&,Rw
The & operator enables the use of MASK and causes bit 5 of the extension word to be set.
The exact algorithm for the use of MASK is as follows:
if extension word, bit [5] = 1, the MASK bit, then
if <ea> = (An)
oa
if <ea> = (An)+
oa
An = (An + 4) & {0xFFFF, MASK}
if <ea> =-(An)
oa
An = (An - 4) & {0xFFFF, MASK}
if <ea> = (d16,An)
oa
Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit
displacement. For auto-addressing modes of post-increment and pre-decrement, the
calculation of the updated An value is also shown.
Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for
circular queue implementations.
MOTOROLA
= An & {0xFFFF, MASK}
= An
= (An - 4) & {0xFFFF, MASK}
= (An + se_d16) & {0xFFFF0x, MASK}
Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC)
Memory Map/Register Set
3-11