Interrupt Mask Register (Imrhn, Imrln); Interrupt Mask Register High (Imrhn); Interrupt Mask Register Low (Imrln); Imrhn Field Descriptions - Motorola ColdFire MCF5281 User Manual

Register Descriptions

10.3.2 Interrupt Mask Register (IMRHn, IMRLn)

The IMRHn and IMRLn registers are each 32 bits in size and provide a bit map for each
interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the request).
The IMRn is set to all ones by reset, disabling all interrupt requests. The IMRn can be read
and written. A write that sets bit 0 of the IMR forces the other 63 bits to be set, disabling
all interrupt sources, and providing a global mask-all capability.
.
31
Field
Reset
R/W
15
Field
Reset
R/W
Figure 10-3. Interrupt Mask Register High (IMRHn)
Bits Name
31–0 INT_MASK
.
31
Field
Reset
R/W
15
Field
Reset
R/W
Figure 10-4. Interrupt Mask Register Low (IMRLn)
10-8
1111_1111_1111_1111
1111_1111_1111_1111
IPSBAR + 0xC08, 0xD08
Table 10-6. IMRHn Field Descriptions
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRHn bit
determines whether an interrupt condition can generate an interrupt. The corresponding
IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
1111_1111_1111_1111
INT_MASK[16:1]
1111_1111_1111_1111
IPSBAR + 0xC0C, 0xD0C
MCF5282 User's Manual
INT_MASK[63:48]
R/W
INT_MASK[47:32]
R/W
Description
INT_MASK[31:16]
R/W
R/W
16
0
16
1 0
MASKALL
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