Line Read Burst-Inhibited, Fast Termination, External Termination; Line Write Burst (2-1-1-1), Internal/External Termination - Motorola ColdFire MCF5281 User Manual

S0
CLKOUT
A[31:0]
R/W
TIP
SIZ[1:0]
TS
CSn, BSn, OE
D[31:0]
TA
Figure 13-15. Line Read Burst-Inhibited, Fast Termination, External Termination
13.4.7.3 Line Write Bus Cycles
Figure 13-16 shows a line access write with zero wait states. It begins like a basic write bus
cycle with data driven one clock after TS. The next pipelined burst data is driven a cycle
after the write data is registered (on the rising edge of S6). Each subsequent burst takes a
single cycle. Note that as with the line read example in Figure 13-12, CSn remain asserted
throughout the burst transfer. This example shows the behavior of the address lines for both
internal and external termination. Note that when external termination is used, the address
lines change with SIZ[1:0].
CLKOUT
A[31:0]
Internal Termination
A[31:0]
External Termination
SIZ[1:0]
R/W, TIP
TS
CSn, OE, BSn
D[31:0]
TA
Figure 13-16. Line Write Burst (2-1-1-1), Internal/External Termination
MOTOROLA
S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0 S1 S4 S5
A[3:2] = 00 A[3:2] = 01
Line
Read
Basic
S0 S1 S2 S3
Chapter 13. External Interface Module (EIM)
A[3:2] = 10
Longword
Read Read
Fast Fast
S4 S5 S6 S7
Write Write
Data Transfer Operation
S6
A[3:2] = 11
Read
Fast
S8 S9 S10 S11
Write Write
13-13
S7