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Chapter 15
Synchronous DRAM Controller Module
This chapter describes configuration and operation of the synchronous DRAM (SDRAM)
controller. It begins with a general description and brief glossary, and includes a description
of signals involved in DRAM operations. The remainder of the chapter describes the
programming model and signal timing, as well as the command set required for
synchronous operations. It also includes extensive examples that the designer can follow to
better understand how to configure the DRAM controller for synchronous operations.
15.1 Overview
The synchronous DRAM controller module provides glueless integration of SDRAM with
the ColdFire product. The key features of the DRAM controller include the following:
• Support for two independent blocks of SDRAM
• Interface to standard SDRAM components
• Programmable SRAS, SCAS, and refresh timing
• Support for 8-, 16-, and 32-bit wide SDRAM blocks
15.1.1 Definitions
The following terminology is used in this chapter:
• SDRAM block: Any group of DRAM memories selected by one of the MCF5282
SRAS[1:0] signals. Thus, the MCF5282 can support two independent memory
blocks. The base address of each block is programmed in the DRAM address and
control registers (DACR0 and DACR1).
• SDRAM: RAMs that operate like asynchronous DRAMs but with a synchronous
clock, a pipelined, multiple-bank architecture, and a faster speed.
• SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit
SDRAM component might be configured as four 512K x 32 banks. Banks are
selected through the SDRAM component's bank select lines.
MOTOROLA
Chapter 15. Synchronous DRAM Controller Module
15-1
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