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Block Diagram
20.2 Block Diagram
System
PR[2:0]
Clock
Divide
Prescaler
by 2
GPTCNTH:GPTCNTL
16-Bit Counter
Channel 0
16-Bit Comparator
GPTC0H:GPTC0L
16-Bit Latch
CHANNEL 1
16-Bit Comparator
GPTC1H:GPTC1L
16-Bit Latch
Channel 2
Channel3
16-Bit Comparator
GPTC3H:GPTC3L
16-Bit Latch
PAOVF
GPTPACNTH:GPTPACNTL
PACLK/65536
PACLK/256
Interrupt
Request
PAOVI
PAOVF
20-2
CLK[1:0]
PACLK
PACLK/256
MUX
PACLK/65536
Clear Counter
TE
C0F
EDG0A
EDG0B
C1F
EDG1A
EDG1B
C3F
EDG3A
EDG3B
MUX
16-Bit Counter
PACLK
Interrupt
PAMOD
Logic
PAI
PAIF
Figure 20-1. GPT Block Diagram
MCF5282 User's Manual
Channel 3 Output Compare
X
TCRE
CxI
CxF
TOF
Interrupt
Logic
TOI
Edge
IOS0
Detect
LOGIC
OM:OL0
TOV0
Edge
IOS1
Detect
LOGIC
OM:OL1
TOV1
Edge
IOS3
Detect
LOGIC
OM:OL3
TOV3
PEDGE
EDGE
DETECT
PAE
Divide-by-64
Interrupt
Request
CH. 0 Capture
PT0
CH. 0 Compare
CH. 1 Capture
PT1
CH. 1 Compare
CH.3 Capture
PA Input
PT3
CH. 3 Compare
PAIF
Divide
System
by 2
Clock
MOTOROLA
SYNCx
Pin
GPTx0
Pin
GPTx1
Pin
GPTx3
Pin
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