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25.4.11 Special Operating Modes
25.4.11.1 Debug Mode
Debug mode is entered by setting the HALT bit in the CANMCR, or by assertion of the
BKPT line. In both cases, the FRZ bit in CANMCR must also be set to allow HALT or
BKPT to place the FlexCAN in debug mode.
Once entry into debug mode is requested, the FlexCAN waits until an intermission or idle
condition exists on the CAN bus, or until the FlexCAN enters the error passive or bus off
state. Once one of these conditions exists, the FlexCAN waits for the completion of all
internal activity. When this happens, the following events occur:
• The FlexCAN stops transmitting/receiving frames.
• The prescaler is disabled, thus halting all CAN bus communication.
• The FlexCAN ignores its Rx pins and drives its Tx pins as recessive.
• The FlexCAN loses synchronization with the CAN bus and the NOTRDY and
FRZACK bits in CANMCR are set.
• The CPU is allowed to read and write the error counter registers.
After engaging one of the mechanisms to place the FlexCAN in debug mode, the user must
wait for the FRZACK bit to be set before accessing any other registers in the FlexCAN,
otherwise unpredictable operation may occur.
To exit debug mode, the BKPT line must be negated or the HALT bit in CANMCR must be
cleared.
Once debug mode is exited, the FlexCAN will resynchronize with the CAN bus by waiting
for 11 consecutive recessive bits before beginning to participate in CAN bus
communication.
25.4.11.2 Low-Power Stop Mode for Power Saving
Before entering low-power stop mode, the FlexCAN will wait for the CAN bus to be in an
idle state, or for the third bit of intermission to be recessive. The FlexCAN then waits for
the completion of all internal activity (except in the CAN bus interface) to be complete.
Afterwards, the following events occur:
• The FlexCAN shuts down its clocks, stopping most internal circuits, thus achieving
maximum power savings.
• The bus interface unit continues to operate, allowing the CPU to access the module
configuration register.
• The FlexCAN ignores its Rx pins and drives its Tx pins as recessive.
• The FlexCAN loses synchronization with the CAN bus, and the STOPACK and
NOTRDY bits in the module configuration register are set.
MOTOROLA
Chapter 25. FlexCAN
Functional Overview
25-17
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