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BIts
31–16
15–0
17.5.4.13 Opcode/Pause Duration Register (OPD)
The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause
duration fields used in transmission of a PAUSE frame. The opcode field is a constant
value, 0x0001. When another node detects a PAUSE frame, that node will pause
transmission for the duration specified in the pause duration field. This register is not reset
and must be initialized by the user.
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-16. Opcode/Pause Duration Register (OPD)
Bits
31–16
15–0
17.5.4.14 Descriptor Individual Upper Address Register (IAUR)
The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit
individual address hash table used in the address recognition process to check for possible
match with the DA field of receive frames with an individual DA. This register is not reset
and must be initialized by the user.
MOTOROLA
Table 17-24. PAUR Field Descriptions
Name
PADDR2
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual
address to be used for exact match, and the Source Address
field in PAUSE frames.
TYPE
Type field in PAUSE frames. These 16-bits are a constant
value of 0x8808.
0000_0000_0000_0001
PAUSE_DUR
IPSBAR + 0x10EC
Table 17-25. OPD Field Descriptions
Name
OPCODE
Opcode field used in PAUSE frames.
These bits are a constant, 0x0001.
PAUSE_DUR
Pause Duration field used in PAUSE frames.
Chapter 17. Fast Ethernet Controller (FEC)
Description
OPCODE
R
Uninitialized
R/W
Description
Programming Model
16
0
17-37
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