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Programmer's Model
25.5.6 Free Running Timer (TIMER)
15
Field
Reset
R/W
Address
Table 25-14 describes the TIMER fields.
Bits
Name
15–0
TIMER The free running timer counter can be read and written by the CPU. The timer starts from zero after
reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the FlexCAN bit-clock. During a message, it increments by one for each bit that
is received or transmitted. When there is no message on the bus, it increments at the nominal bit rate.
The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. The
captured value is written into the "time stamp" entry in a message buffer after a successful reception
or transmission of a message.
25.5.7 Rx Mask Registers
These registers are used as acceptance masks for received frame IDs. 3 masks are defined:
A global mask, used for Rx buffers 0-13, and 2 more separate masks for buffers 14 and 15.
Mask bit = 0: The corresponding incoming ID bit is "don't care".
Mask bit = 1: The corresponding ID bit is checked against the incoming ID bit, to see if a
match exists.
Note that these masks are used both for Standard and Extended ID formats. The value of
mask registers should NOT be changed while in normal operation, as locked frames which
matched a MB through a mask, may be transferred into the MB (upon release) but may no
longer match.
Table 25-15. Mask examples for Normal/Extended Messages
MB2-Id
MB3-Id
MB4-Id
MB5-Id
25-26
Figure 25-11. Free Running Timer (TIMER)
Table 25-14. TIMER Field Descriptions
Base ID
ID28.................ID18
1 1 1 1 1 1 1 1 0 0 0
1 1 1 1 1 1 1 1 0 0 0
0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 1 1 1 0 1
MCF5282 User's Manual
TIMER
0000_0000_0000_0000
R/W
IPSBAR + 0x1C_000A
Description
I
Extended ID
D
ID17......................................ID0
E
0
1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0
Match
MOTOROLA
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