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Chapter 8
System Control Module (SCM)
This section details the functionality of the System Control Module (SCM) which provides
the programming model for the System Access Control Unit (SACU), the system bus
arbiter, a 32-bit core watchdog timer (CWT), and the system control registers and logic.
Specifically, the system control includes the internal peripheral system (IPS) base address
register (IPSBAR), the processor's dual-port RAM base address register (RAMBAR), and
system control registers that include the core watchdog timer control.
8.1
Overview
The SCM provides the control and status for a variety of functions including base
addressing and address space masking for both the IPS peripherals and resources (IPSBAR)
and the ColdFire core memory spaces (RAMBAR). The MCF5282 CPU core supports two
memory banks, one for the internal SRAM and the other for the internal Flash.
The SACU provides the mechanism needed to implement secure bus transactions to the
system address space.
The programming model for the system bus arbitration resides in the SCM. The SCM
sources the necessary control signals to the arbiter for bus master management.
The CWT provides a means of preventing system lockup due to uncontrolled software
loops via a special software service sequence. If periodic software servicing action does not
occur, the CWT times out with a programmed response (system reset or interrupt) to allow
recovery or corrective action to be taken.
8.2
Features
The SCM includes these distinctive features:
• IPS base address register (IPSBAR)
— Base address location for 1-Gbyte peripheral space
— User control bits
• Processor-local memory base address register (RAMBAR)
• System control registers
MOTOROLA
Chapter 8. System Control Module (SCM)
8-1
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