Motorola ColdFire MCF5281 User Manual page 512

Interface Features
• Acknowledge bit generation/detection
• Bus-busy detection
Figure 24-1 is a block diagram of the I
Registers and ColdFire Interface
2
I C Frequency
Divider Register
(IFDR)
Clock
Control
Input
Sync
Figure 24-1 shows the relationships of the I
2
• I C address register (I2ADR)
2
• I C frequency divider register (I2FDR)
2
• I C control register (I2CR)
2
• I C status register (I2SR)
2
I C data I/O register (I2DR)These registers are described in Section 24.5, "Programming
Model."
24-2
2
C module.
IRQ
2 2
I C Control I C Status
Register Register
(I2CR) (I2SR)
Start, Stop,
and
Arbitration
Control
SCL SDA
2
Figure 24-1. I C Module Block Diagram
2
MCF5282 User's Manual
Internal Bus
Address
Address Decode
2
I C Data
I/O Register
(I2DR)
In/Out
Data
Shift
Register
Address
Compare
C registers, listed below:
Data
Data MUX
2
I C Address
Register
(IADR)
MOTOROLA