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Overview
Table 14-2. MCF5282 Alphabetical Signal Index (Continued)
Abbreviation
QADC analog supply
QSPI_CLK
QSPI_CS[3:0]
QSPI_DIN
QSPI_DOUT
R/W
RCON
RSTI
RSTO
SCAS
SCKE
SCL
SDA
SDRAM_CS[1:0]
SIZ[1:0]
SRAS
VSTBY
SYNCA/SYNCB
TA
TEA
TEST
TCK
TIP
TS
UCTS[1:0]
URTS[1:0]
URXD[2:0]
14-10
Supplies positive power to the ESD structures in the QADC
pads.
Provides the serial clock from the QSPI.
Provide QSPI peripheral chip selects.
Provides serial data to the QSPI.
Provides serial data from the QSPI.
Indicates the direction of the data transfer on the bus.
Reset configuration select.
Asserted to enter reset exception processing.
Automatically asserted with RSTI. Negation indicates that the
PLL has regained its lock.
SDRAM synchronous column address strobe.
SDRAM clock enable.
2
Clock signal for the I
C interface.
2
Data input/output for the I
Interface to the chip-select lines of the SDRAMs within a
memory block.
Specify the data access size of the current external bus
reference.
SDRAM synchronous row address strobe.
Provides standby voltage to RAM array if VDD is lost.
Clear the timer's clock, providing a means of synchronization
to externally clocked or timed events.
Indicates that the external data transfer is complete and should
be asserted for one CLKOUT cycle.
Indicates that an error condition exists for the bus transfer.
Reserved, should be connected to VSS.
JTAG test logic clock.
Asserted to indicate that a bus transfer is in progress. Negated
during idle bus cycles.
Asserted during the first CLKOUT cycle of a transfer when
address and attributes are valid.
Signals UART that it can begin data transmission.
Automatic UART request to send outputs.
Receiver serial data inputs.
MCF5282 User's Manual
Function
C interface.
I/O
I
O
O
I
O
I/O
I
I
O
O
O
I/O
I/O
O
O
O
I
I
I
I
I
I
O
O
I
O
I
MOTOROLA
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