Table of Contents
Advertisement
Functional Description
17.4.6 FEC Frame Transmission
The Ethernet transmitter is designed to work with almost no intervention from software.
Once ECR[ETHER_EN] is asserted and data appears in the transmit FIFO, the Ethernet
MAC is able to transmit onto the network.
When the transmit FIFO fills to the watermark (defined by the TFWR), the MAC transmit
logic will assert ETXEN and start transmitting the preamble (PA) sequence, the start frame
delimiter (SFD), and then the frame information from the FIFO. However, the controller
defers the transmission if the network is busy (ECRS asserts). Before transmitting, the
controller waits for carrier sense to become inactive, then determines if carrier sense stays
inactive for 60 bit times. If so, the transmission begins after waiting an additional 36 bit
times (96 bit times after carrier sense originally became inactive). See Section 17.4.14.1,
"Transmission Errors" for more details.
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet
controller follows the specified backoff procedures and attempts to retransmit the frame
until the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the
transmit frame, so that they do not have to be retrieved from system memory in case of a
collision. This improves bus utilization and latency in case immediate retransmission is
necessary.
When all the frame data has been transmitted, the FCS (Frame Check Sequence or 32-bit
Cyclic Redundancy Check, CRC) bytes are appended if the TC bit is set in the transmit
frame control word. If the ABC bit is set in the transmit frame control word, a bad CRC will
be appended to the frame data regardless of the TC bit value. Following the transmission
of the CRC, the Ethernet controller writes the frame status information to the MIB block.
Short frames are automatically padded by the transmit logic (if the TC bit in the transmit
buffer descriptor for the end of frame buffer = 1).
Both buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the
settings in the EIMR.
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and
XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes the BABT interrupt will
be asserted, however the entire frame will be transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When
the TCR[GTS] is set, the FEC transmitter stops immediately if transmission is not in
progress; otherwise, it continues transmission until the current frame either finishes or
terminates with a collision. After the transmitter has stopped the GRA (graceful stop
complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes transmission with
the next frame.
The Ethernet controller transmits bytes least significant bit first.
MOTOROLA
Chapter 17. Fast Ethernet Controller (FEC)
17-9
Advertisement
Table of Contents
