Cache Configuration As Defined By Cacr[31, 23, 22]; Cache Invalidate All As Defined By Cacr[23, 22, 21, 20] - Motorola ColdFire MCF5281 User Manual

Motorola microcontroller user's manual
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Cache Programming Model
Bits
Name
3–2
Reserved, should be cleared.
1–0
CLNF
Cache line fill. These bits control the size of the memory request the cache issues to the bus controller
for different initial instruction line access offsets. See Table 4-7 for external fetch size based on miss
address and CLNF.
Table 4-5 shows the relationship between CACR bits 31, 23, and 22 and the cache
configuration.
Table 4-5. Cache Configuration as Defined by CACR[31, 23, 22]
CACR[31] CACR[23] CACR[22]
0
x
1
0
1
0
1
1
Table 4-6 shows the relationship between CACR bits 23, 22, 21 and 20 and setting the
cache invalidate all bit.
Table 4-6. Cache Invalidate All as Defined by CACR[23, 22, 21, 20]
CACR[23] CACR[22] CACR[21] CACR[20]
0
0
0
0
0
0
0
0
1
0
0
1
4-10
Table 4-4. CACR Field Descriptions (continued)
Configuration
x
N/A
0
Split Instruction/
Data Cache
1
Instruction Cache
0
Data Cache
0
0
Split Instruction/
Data Cache
0
1
Split Instruction/
Data Cache
1
0
Split Instruction
Data Cache
1
1
Split Instruction/
Data Cache
x
x
Instruction Cache
x
x
Data Cache
MCF5282 User's Manual
Description
Cache is completely disabled
1 KByte direct-mapped instruction cache (uses lower half
of tag and storage arrays) and 1 KByte direct-mapped
write-through data cache (uses upper half of tag and storage
arrays)
2 KByte direct-mapped instruction cache (uses all of tag
and storage arrays)
2 KByte direct-mapped write-through data cache (uses all
of tag and storage arrays)
Configuration
Invalidate all entries in both 1 KByte instruction
cache and 1 KByte data cache
Invalidate only 1 KByte data cache
Invalidate only 1 KByte instruction cache
No invalidate
Invalidate 2 KByte instruction cache
Invalidate 2 KByte data cache
Description
Operation
MOTOROLA

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