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Memory Map and Registers
20.5.12 GPT Flag Register 1 (GPTFLG1)
Field
Reset
R/W
Address
Bit(s)
Name
7–4
—
3–0
CnF
20.5.13 GPT Flag Register 2 (GPTFLG2)
Field
TOF
Reset
R/W
Address
Bit(s)
Name
7
TOF
6–4
—
3–0
CnF
Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT
flag register 2.
20-12
7
6
5
—
IPSBAR + 0x1A_000E, 0x1B_000E
Figure 20-14. GPT Flag Register 1 (GPTFLG1)
Table 20-15. GPTFLG1 Field Descriptions
Reserved, should be cleared.
Channel flags. A channel flag is set when an input capture or output compare event
occurs. These bits are read anytime, write anytime (writing 1 clears the flag, writing 0
has no effect).
Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture read
or an output compare write clears the corresponding channel flag. When a channel flag
is set, it does not inhibit subsequent output compares or input captures.
7
6
5
—
IPSBAR + 0x1A_000F, 0x1B_000F
Figure 20-15. GPT Flag Register 2 (GPTFLG2)
Table 20-16. GPTFLG2 Field Descriptions
Timer overflow flag. Set when the GPT counter rolls over from 0xFFFF to 0x0000. If
the TOI bit in GPTSCR2 is also set, TOF generates an interrupt request. This bit is read
anytime, write anytime (writing 1 clears the flag, and writing 0 has no effect).
1 Timer overflow
0 No timer overflow
Note: When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does
not get set even though the GPT counter registers go from 0xFFFF to 0x0000. When
TOF is set, it does not inhibit subsequent overflow events.
Reserved, should be cleared.
Channel flags. A channel flag is set when an input capture or output compare event
occurs. These bits are read anytime, write anytime (writing 1 clears the flag, writing 0
has no effect).
MCF5282 User's Manual
4
3
CF
0000_0000
R/W
Description
4
3
CF
0000_0000
R/W
Description
0
0
MOTOROLA
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