Synthesizer Control Register (Syncr); Register Descriptions; Syncr Field Descriptions - Motorola ColdFire MCF5281 User Manual

Memory Map and Registers
9.6.2

Register Descriptions

This subsection provides a description of the clock module registers.
9.6.2.1

Synthesizer Control Register (SYNCR)

15
Field LOLRE
Reset
R/W
7
Field LOCEN
Reset
R/W
Address
Figure 9-3. Synthesizer Control Register (SYNCR)
Bit(s) Name
15 LOLRE
9-6
14 13
MFD2 MFD1
6 5
DISCLK FWKUP
R/W
IPSBAR + 0x0012_0000
Table 9-4. SYNCR Field Descriptions
Loss of lock reset enable. Determines how the system handles a loss of lock indication.
When operating in normal mode or 1:1 PLL mode, the PLL must be locked before
setting the LOLRE bit. Otherwise reset is immediately asserted. To prevent an
immediate reset, the LOLRE bit must be cleared before writing the MFD[2:0] bits or
entering stop mode with the PLL disabled.
1 Reset on loss of lock
0 No reset on loss of lock
Note: In external clock mode, the LOLRE bit has no effect.
MCF5282 User's Manual
12 11
MFD0 LOCRE RFD2
0010_0001
R/W
4 3
— STPMD1 STPMD0
0000_0000
R R/W
Description
10 9 8
RFD1 RFD0
2 1 0
— —
R
MOTOROLA