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Table 17-11. MIB Counters Memory Map (continued)
IPSBAR
Offset
0x1290
0x1294
0x1298
0x129C
0x12A0
0x12A4
0x12A8
0x12AC
0x12B0
0x12B4
0x12B8
0x12BC
0x12C0
0x12C4
0x12C8
0x12CC
0x12D0
0x12D4
0x12D8
0x12DC
0x12E0
17.5.4 Registers
The following sections describe each register in detail.
17.5.4.1 Ethernet Interrupt Event Register (EIR)
When an event occurs that sets a bit in the EIR, an interrupt will be generated if the
corresponding bit in the interrupt mask register (EIMR) is also set. The bit in the EIR is
cleared if a one is written to that bit position; writing zero has no effect. This register is
cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error
interrupts, and internal error interrupts. Interrupts which may occur in normal operation are
GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected
MOTOROLA
Mnemonic
RMON_R_CRC_ALIGN
RMON_R_UNDERSIZE
RMON_R_OVERSIZE
RMON_R_FRAG
RMON_R_JAB
RMON_R_RESVD_0
RMON_R_P64
RMON_R_P65TO127
RMON_R_P128TO255
RMON_R_P256TO511
RMON_R_P512TO1023
RMON_R_P1024TO2047
RMON_R_P_GTE2048
RMON_R_OCTETS
IEEE_R_DROP
IEEE_R_FRAME_OK
IEEE_R_CRC
IEEE_R_ALIGN
IEEE_R_MACERR
IEEE_R_FDXFC
IEEE_R_OCTETS_OK
Chapter 17. Fast Ethernet Controller (FEC)
Description
RMON Rx Packets w CRC/Align error
RMON Rx Packets < 64 bytes, good crc
RMON Rx Packets > MAX_FL bytes, good crc
RMON Rx Packets < 64 bytes, bad crc
RMON Rx Packets > MAX_FL bytes, bad crc
RMON Rx 64 byte packets
RMON Rx 65 to 127 byte packets
RMON Rx 128 to 255 byte packets
RMON Rx 256 to 511 byte packets
RMON Rx 512 to 1023 byte packets
RMON Rx 1024 to 2047 byte packets
RMON Rx packets w > 2048 bytes
RMON Rx Octets
Count of frames not counted correctly
Frames Received OK
Frames Received with CRC Error
Frames Received with Alignment Error
Receive Fifo Overflow count
Flow Control Pause frames received
Octet count for Frames Rcvd w/o Error
Programming Model
17-23
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