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15.3 SDRAM Example
This example interfaces a 512K x 32-bit x 4 bank SDRAM component to a MCF5282
operating at 40 MHz. Table 15-25 lists design specifications for this example.
Speed grade (-8E)
10 rows, 8 columns
Two bank-select lines to access four internal banks
-to-read/write delay (t
ACTV
Period between auto-refresh and
command to precharge command (t
ACTV
Precharge command to
Last data input to
Auto-refresh period for 4096 rows (t
MOTOROLA
CLKOUT
A[31:0]
SRAS, SCAS
DRAMW
D[31:0]
SD_CS[1] or [0]
Figure 15-10. Mode Register Set (
Table 15-25. SDRAM Example Specifications
Parameter
)
RCD
command (t
ACTV
RAS
command (t
ACTV
RP
command (t
)
PALL
RWL
)
REF
Chapter 15. Synchronous DRAM Controller Module
MRS
) Command
MRS
40 MHz (25-ns period)
20 ns (min.)
)
70 ns
RC
)
48 ns (min.)
)
20 ns (min.)
1 bus clock (25 ns)
64 mS
SDRAM Example
Specification
15-19
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