Table of Contents
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Table
Number
1-1
Cache Configuration ..................................................................................................... 1-8
2-1
CCR Field Descriptions ................................................................................................ 2-4
2-2
SR Field Descriptions ................................................................................................... 2-6
2-3
ColdFire CPU Registers................................................................................................ 2-8
2-4
ISA Revision A+ New Instructions ............................................................................ 2-10
2-5
Exception Vector Assignments................................................................................... 2-11
2-6
Format Field Encodings.............................................................................................. 2-12
2-7
Fault Status Encodings................................................................................................ 2-13
2-8
D0 Hardware Configuration Info Field Description................................................... 2-18
2-9
D1 Local Memory Hardware Configuration Information Field Description ............. 2-19
2-10
Misaligned Operand References ................................................................................. 2-22
2-11
Move Byte and Word Execution Times ..................................................................... 2-23
2-12
Move Long Execution Times .................................................................................... 2-23
2-13
One Operand Instruction Execution Times ................................................................ 2-24
2-14
Two Operand Instruction Execution Times................................................................ 2-24
2-15
Miscellaneous Instruction Execution Times............................................................... 2-26
2-16
EMAC Instruction Execution Times .......................................................................... 2-27
2-17
General Branch Instruction Execution Times............................................................. 2-28
2-18
BRA, Bcc Instruction Execution Times ..................................................................... 2-28
3-1
MACSR Field Descriptions .......................................................................................... 3-7
3-2
Summary of S/U, F/I, and R/T Control Bits ................................................................. 3-8
3-3
EMAC Instruction Summary ...................................................................................... 3-12
4-1
Initial Fetch Offset vs. CLNF Bits................................................................................ 4-5
4-2
Instruction Cache Operation as Defined by CACR[31, 10] ......................................... 4-6
4-3
Memory Map of Cache Registers ................................................................................. 4-7
4-4
CACR Field Descriptions ............................................................................................. 4-8
4-5
Cache Configuration as Defined by CACR[31, 23, 22] ............................................. 4-10
4-6
Cache Invalidate All as Defined by CACR[23, 22, 21, 20]........................................ 4-10
4-7
External Fetch Size Based on Miss Address and CLNF ............................................ 4-11
4-8
ACR Field Descriptions.............................................................................................. 4-11
5-1
SRAM Base Address Register ...................................................................................... 5-2
5-2
Typical RAMBAR Setting Examples........................................................................... 5-4
6-1
CFM Configuration Field ............................................................................................ 6-5
6-2
FLASHBAR Field Descriptions ................................................................................... 6-7
6-3
CFM Register Address Map ......................................................................................... 6-8
6-4
CFMCR Field Descriptions .......................................................................................... 6-9
MOTOROLA
TABLES
Title
Tables
Page
Number
xxxiii
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