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Functional Description
Both internal and external loopback are configured using combinations of the LOOP and
DRT bits in the RCR register and the FDEN bit in the TCR register.
For both internal and external loopback set FDEN = 1.
For internal loopback set RCR[LOOP] = 1 and RCR[DRT] = 0. ETXEN and ETXER will
not assert during internal loopback. During internal loopback, the transmit/receive data rate
is higher than in normal operation because the internal system clock is used by the transmit
and receive blocks instead of the clocks from the external transceiver. This will cause an
increase in the required system bus bandwidth for transmit and receive data being DMA'd
to/from external memory. It may be necessary to pace the frames on the transmit side and/or
limit the size of the frames to prevent transmit FIFO underrun and receive FIFO overflow.
For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external
transceiver for loopback.
17.4.14 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the
FEC RxBDs, the EIR register, and the MIB block counters.
17.4.14.1 Transmission Errors
17.4.14.1.1 Transmitter Underrun
If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting.
All remaining buffers for that frame are then flushed and closed. The UN bit is set in the
EIR. The FEC will then continue to the next transmit buffer descriptor and begin
transmitting the next frame.
The "UN" interrupt will be asserted if enabled in the EIMR register.
17.4.14.1.2 Retransmission Attempts Limit Expired
When this error occurs, the FEC terminates transmission. All remaining buffers for that
frame are flushed and closed, and the RL bit is set in the EIR. The FEC will then continue
to the next transmit buffer descriptor and begin transmitting the next frame.
The "RL" interrupt will be asserted if enabled in the EIMR register.
17.4.14.1.3 Late Collision
When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC
terminates transmission. All remaining buffers for that frame are flushed and closed, and
the LC bit is set in the EIR register. The FEC will then continue to the next transmit buffer
descriptor and begin transmitting the next frame.
The "LC" interrupt will be asserted if enabled in the EIMR register.
17-18
MCF5282 User's Manual
MOTOROLA
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