Interrupt Force Registers (Intfrchn, Intfrcln); Interrupt Force Register High (Intfrchn); Intfrchn Field Descriptions; Imrln Field Descriptions - Motorola ColdFire MCF5281 User Manual

Bits Name
31–1 INT_MASK
0 MASKALL

10.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)

The INTFRCHn and INTFRCLn registers are each 32 bits in size and provide a mechanism
to allow software generation of interrupts for each possible source for functional or debug
purposes. The system design may reserve one or more sources to allow software to
self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate
request) in the appropriate INTFRCn register. The assertion of an interrupt request via the
INTFRCn register is not affected by the interrupt mask register. The INTFRCn register is
cleared by reset.
31
Field
Reset
R/W
15
Field
Reset
R/W
Figure 10-5. Interrupt Force Register High (INTFRCHn)
Bits Name
31–0 INTFRC Interrupt force. Allows software generation of interrupts for each possible source for functional or
debug purposes.
0 No interrupt forced on corresponding interrupt source
1 Force an interrupt on the corresponding source
MOTOROLA
Table 10-7. IMRLn Field Descriptions
Interrupt mask. Each bit corresponds to an interrupt source. The corresponding
IMRLn bit determines whether an interrupt condition can generate an interrupt.
The corresponding IPRLn bit reflects the state of the interrupt signal even if the
corresponding IMRLn bit is set.
0 The corresponding interrupt source is not masked
1 The corresponding interrupt source is masked
Mask all interrupts. Setting this bit will force the other 63 bits of the IMRHn and
IMRLn to ones, disabling all interrupt sources, and providing a global mask-all
capability.
INTFRCH[63:48]
0000_0000_0000_0000
INTFRCH[47:32]
0000_0000_0000_0000
IPSBAR + 0xC10, 0xD10
Table 10-8. INTFRCHn Field Descriptions
Chapter 10. Interrupt Controller Modules
Description
R/W
R/W
Description
Register Descriptions
16
0
10-9