Gpt Compare Force Register (Gpcforc); Gpt Input Compare Force Register (Gpcforc); Gptios Field Descriptions; Gptcforc Field Descriptions - Motorola ColdFire MCF5281 User Manual

Memory Map and Registers
Bit(s) Name
7–4 —
3–0 IOS

20.5.2 GPT Compare Force Register (GPCFORC)

Field
Reset
R/W
Address
Figure 20-3. GPT Input Compare Force Register (GPCFORC)
Bit(s) Name
7–4 —
3–0 FOC
A successful channel 3 output compare overrides any compare
on channels 2:0. For each OC3M bit that is set, the output
compare action reflects the corresponding OC3D bit.

20.5.3 GPT Output Compare 3 Mask Register (GPTOC3M)

Field
Reset
R/W
Address
Figure 20-4. GPT Output Compare 3 Mask Register (GPTOC3M)
20-6
Table 20-4. GPTIOS Field Descriptions
Reserved, should be cleared.
I/O select. The IOS[3:0] bits enable input capture or output compare operation for the
corresponding timer channels. These bits are read anytime (always read 0x00), write
anytime.
1 Output compare enabled
0 Input capture enabled
7
—
IPSBAR + 0x1A_00001, 0x1B_0001
Table 20-5. GPTCFORC Field Descriptions
Reserved, should be cleared.
Force output compare.Setting an FOC bit causes an immediate output compare on the
corresponding channel. Forcing an output compare does not set the output compare
flag. These bits are read anytime, write anytime.
1 Force output compare
0 No effect
7
—
IPSBAR + 0x1A_0002, 0x1B_0002
MCF5282 User's Manual
Description
4 3
0000_0000
R/W
Description
NOTE
4 3
0000_0000
R/W
0
FOC
0
OC3M
MOTOROLA