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Signal Connection Considerations
• Any conversion in progress for a queue is aborted when that queue's operating mode
is changed to disabled. Putting a queue into the disabled mode does not power down
the converter.
• Changing a queue's operating mode to another valid mode aborts any conversion in
progress. The queue restarts at its beginning once an appropriate trigger event
occurs.
• For low-power operation, the stop bit can be set to prepare the module for a loss of
clocks. The QADC aborts any conversion in progress when stop mode is entered.
• When the QADC debug bit is set and the CPU enters background debug mode, the
QADC freezes at the end of the conversion in progress. After leaving debug mode,
the QADC resumes queue execution beginning with the next CCW entry. Refer to
Section 27.3.1" for more information.
27.8.11 Result Word Table
The result word table is a 64 half-word (128 byte) long by 10-bit wide RAM. An entry is
written by the QADC after completing an analog conversion specified by the corresponding
CCW table entry. The result word table can be read or written, but in normal operation is
only read to obtain analog conversions from the QADC. Unimplemented bits read as 0s and
writes have no effect.
Although the result RAM can be written, some write
operations, like bit manipulation, may not operate as expected
because the hardware cannot access a true 16-bit value.
While there is only one result word table, the half-word (16-bit) data can be accessed in
three different data formats:
• Right justified with 0s in the higher order unused bits
• Left justified with the most significant bit inverted to form a sign bit, and 0s in the
unused lower order bits
• Left justified with 0s in the lower order unused bits
The left justified, signed format corresponds to a half-scale, offset binary, two's
complement data format. The address used to read the result table determines the data
alignment format. All write operations to the result word table are right justified.
27.9 Signal Connection Considerations
The QADC requires accurate, noise-free input signals for proper operation. This section
discusses the design of external circuitry to maximize QADC performance.
27-62
NOTE
MCF5282 User's Manual
MOTOROLA
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