Mode Register Initialization; Mode Register Mapping To Mcf5282 A[31:0] - Motorola ColdFire MCF5281 User Manual

15.3.5 Mode Register Initialization

When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register
setting is read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the
corresponding MCF5282 address pins must be determined while being aware of masking
requirements.
Table 15-30 lists the desired initialization setting:
MCF5282 Pins
Next, this information is mapped to an address to determine the hexadecimal value.
31 30 29
Field
Setting
(hex)
15 14 13
Field
Setting
(hex)
Table 15-31. Mode Register Mapping to MCF5282 A[31:0]
Although A[31:20] corresponds to the address programmed in DACR0, according to how
DACR0 and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before
the mode register bit is set, DMR0[19] must be set to enable masking.
MOTOROLA
Table 15-30. Mode Register Initialization
SDRAM Pins
A20 A10
A19 A9
A18 A8
A17 A7
A9 A6
A10 A5
A11 A4
A12 A3
A13 A2
A14 A1
A15 A0
28 27 26 25
xxxx_xxxx_xxxx_000x
12 11 10 9
0000_100x_xxxx_xxxx
Chapter 15. Synchronous DRAM Controller Module
Mode Register Initialization
Reserved
WB
Opmode
Opmode
CASL
CASL
CASL
BT
BL
BL
BL
24 23 22 21
0000
8 7 6 5
0800
SDRAM Example
X
0
0
0
0
0
1
0
0
0
0
20 19 18 17
4 3 2 1
15-23
16
0
V