Receiver Timing - Motorola ColdFire MCF5281 User Manual

After the stop bit is detected, the receiver immediately looks for the next start bit. However,
if a non-zero character is received without a stop bit (framing error) and URXD remains
low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a
new start bit were detected. Parity error, framing error, overrun error, and received break
conditions set the respective PE, FE, OE, RB error and break flags in the USRn at the
received character boundary and are valid only if USRn[RxRDY] is set.
If a break condition is detected (URXD is low for the entire character including the stop
bit), a character of all zeros is loaded into the receiver holding register and
USRn[RB,RxRDY] are set. URXD must return to a high condition for at least one-half bit
time before a search for the next start bit begins.
The receiver detects the beginning of a break in the middle of a character if the break
persists through the next character time. If the break begins in the middle of a character, the
receiver places the damaged character in the Rx FIFO stack and sets the corresponding
USRn error bits and USRn[RxRDY]. Then, if the break lasts until the next character time,
the receiver places an all-zero character into the Rx FIFO and sets USRn[RB,RxRDY].
Figure 23-21 shows receiver functional timing.
UTXDn C1
Receiver
Enabled
USRn[RxRDY]
USRn[FFULL]
internal
module
select
Overrun
USRn[OE]
Manually asserted first time,
4
URTSn
automatically negated if overrun occurs
UOP0[RTS] = 1
23.5.2.3 FIFO Stack
The FIFO stack is used in the UART's receive buffer logic. The stack consists of three
receiver holding registers. The receive buffer consists of the FIFO and a receiver shift
register connected to the URXD (see Figure 23-19). Data is assembled in the receiver shift
MOTOROLA
C2 C3
Status
Data
(C1)
Figure 23-21. Receiver Timing
Chapter 23. UART Modules
C4 C5 C6
Status
Data
C5 will
(C2)
be lost
Operation
C8
C7
C6, C7, and C8 will be lost
Status Status
Data Data
(C3) (C4)
Reset by
command
Automatically asserted
when ready to receive
23-23