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Recall that when QS = 0, both queues are disabled; when QS = 8, queue 1 is active and
queue 2 is idle; and when QS = 4; queue 1 is paused and queue 2 is disabled.
CONVERSION TIME
= 14 QCLKS
QCLK
TRIG1
EOC
QS
0
CWP
LAST
CWPQ1
LAST
Q1 RES
Figure 27-46. External Positive Edge Trigger Mode Timing with Pause
A time separator is provided between the triggers and the end of conversion (EOC). The
relationship to QCLK displayed is not guaranteed.
CWPQ1 and CWPQ2 typically lag CWP and only match CWP when the associated queue
is inactive. Another way to view CWPQ1 and CWPQ2 is that these registers update when
EOC triggers the write to the result register.
For the CCW with the pause bit set (CCW0), CWP does not increment until triggered. For
the CCW with the pause bit clear (CCW1), the CWP increments with the EOC.
The conversion results Q1 RESx show the result associated with CCWx, such that R0
represents the result associated with CCW0.
Figure 27-47 shows the timing for conversions in externally gated single-scan with same
assumptions in example 1 except:
• No pause bits set in any CCW
• Externally gated single scan mode for Q1
• Single scan enable bit (SSE1) is set.
When the gate closes and opens again, the conversions start with the first CCW in Q1.
MOTOROLA
TIME BETWEEN
TRIGGERS
8
CCW0
Chapter 27. Queued Analog-to-Digital Converter (QADC)
Signal Connection Considerations
4
CCW0
R0
CONVERSION TIME
= 14 QCLKS
8
CCW1
CCW2
CCW1
R1
27-65
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