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Memory Map and Registers
Some control register bits are implemented as write-once bits. These bits are always
readable, but once the bit has been written, additional writes have no effect, except during
debug and test operations.
Some write-once bits can be read and written while in debug mode. When debug mode is
exited, the chip configuration module resumes operation based on the current register
values. If a write to a write-once register bit occurs while in debug mode, the register bit
remains writable on exit from debug or test mode. Table 30-2 shows the accessibility of
write-once bits.
All configurations
Debug operation (all modes)
Master mode
Single-chip mode
30.5.2 Memory Map
IPSBAR Offset
0x0011_0004
0x0011_0008
Reset Configuration Register (RCON)
0x0011_000c
0x0011_0010
1
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle termination
transfer error.
2
See Chapter 7, "Power Management," for a description of the LPCR. It is shown here only to warn against accidental writes to this register.
3
Writing to reserved addresses with values other than 0 could put the device in a test mode; reading returns 0s.
4
Accessing an unimplemented address has no effect and causes a cycle termination transfer error.
To safeguard against unintentionally activating test logic, write
0x0000 to the above reserved location during initialization
(immediately after reset) to lock out test features. Setting any bits in
the CCR may lead to unpredictable results.
30-4
Table 30-2. Write-Once Bits Read/Write Accessibility
Configuration
Table 30-3. Chip Configuration Module Memory Map
Bits 31–16
Chip Configuration Register (CCR)
MCF5282 User's Manual
Read/Write Access
Read-always
Write-always
Write-once
Write-once
Low-Power Control Register (LPCR)
Chip Identification Register (CIR)
3
Reserved
4
Unimplemented
NOTE
Bits 15–0
2
MOTOROLA
1
Access
S
S
S
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