Table of Contents
Advertisement
MCF5282 External Signals
pin can also be configured as an output signal, MA0, to select the output of the external
multiplexer.
This pin can also be configured as GPIO PQA0.
14.2.13.6 QADC Analog Input (AN53/MA1)
This PQA signal is the direct analog input AN53. When using external multiplexing this
pin can also be configured as an output signal, MA1, to select the output of the external
multiplexer.
This pin can also be configured as GPIO PQA1.
14.2.13.7 QADC Analog Input (AN55/TRIG1)
This PQA signal is the direct analog input AN55. This pin can also be configured as an
input signal, TRIG1, to trigger the execution of one of the two queues.
This pin can also be configured as GPIO PQA3.
14.2.13.8 QADC Analog Input (AN56/TRIG2)
This PQA signal is the direct analog input AN56. This pin can also be configured as an
input signal, TRIG2, to trigger the execution of one of the two queues.
This pin can also be configured as GPIO PQA4.
14.2.14 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface
to the BDM logic.
14.2.14.1 JTAG_EN
This input signal is used to select between multiplexed debug module and JTAG signals at
reset. If JTAG_EN is low, the part is in normal and background debug mode (BDM); if it
is high, it is in normal and JTAG mode.
14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST)
Debug mode operation: DSCLK is selected. DSCLK is the development serial clock for the
serial interface to the debug module. The maximum DSCLK frequency is 1/5 CLKIN.
JTAG mode operation: TRST is selected. TRST asynchronously resets the internal JTAG
controller to the test logic reset state, causing the JTAG instruction register to choose the
bypass instruction. When this occurs, JTAG logic is benign and does not interfere with
normal MCF5282 functionality.
Although TRST is asynchronous, Motorola recommends that it makes an
14-30
MCF5282 User's Manual
MOTOROLA
Advertisement
Table of Contents
