Motorola ColdFire MCF5281 User Manual page 176

Functional Description
7.3.2.5 SDRAM Controller (SDRAMC)
SDRAMC operation is unaffected by either the wait or doze modes; however, the
SDRAMC is disabled by stop mode. Since all clocks to the SDRAMC are disabled by stop
mode, the SDRAMC will not generate refresh cycles.
To prevent loss of data the SDRAM should be placed in self-refresh mode by setting
DCR[IS] before entering stop mode. The SDRAM self-refresh mode allows the SDRAM
to enter a low-power state where internal refresh operations are used to maintain the
integrity of the data stored in the SDRAM.
When stop mode is exited clearing the DCR[IS] bit will cause the SDRAM to exit the
self-refresh mode and allow bus cycles to the SDRAM to resume.
The SDRAM is inaccessible while in the self-refresh mode.
Therefore, if stop mode is used the vector table and any
interrupt handlers that could wake the processor should not be
stored in or attempt to access SDRAM.
7.3.2.6 Chip Select Module
In wait and doze modes, the chip select module continues operation but does not generate
interrupts; therefore it cannot bring a device out of a low-power mode. This module is
stopped in stop mode.
7.3.2.7 DMA Controller (DMAC0–DMA3)
In wait and doze modes, the DMA controller is capable of bringing the device out of a
low-power mode by generating an interrupt either upon completion of a transfer or upon an
error condition. The completion of transfer interrupt is generated when DMA interrupts are
enabled by the setting of the DCR[INT] bit, and an interrupt is generated when the
DSR[DONE] bit is set. The interrupt upon error condition is generated when the DCR[INT]
bit is set, and an interrupt is generated when either the CE, BES or BED bit in the DSR
becomes set.
The DMA controller is stopped in stop mode and thus cannot cause an exit from this
low-power mode.
7.3.2.8 UART Modules (UART0, UART1, and UART2)
In wait and doze modes, the UART may generate an interrupt to exit the low-power modes.
• Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART
functions.
• The UARTs are unaffected by wait mode and may generate an interrupt to exit this
mode.
7-8
NOTE
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