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Table 17-10. FEC Register Memory Map (continued)
IPSBAR
Offset
0x1084
0x10C4
0x10E4
0x10E8
0x10EC
0x1118
0x111C
0x1120
0x1124
0x1144
0x114C
0x1150
0x1180
0x1184
0x1188
17.5.3 MIB Block Counters Memory Map
Table 17-11 defines the MIB Counters memory map which defines the locations in the MIB
RAM space where hardware maintained counters reside. These fall in the 0x1200-0x13FF
address offset range. The counters are divided into two groups.
RMON counters are included which cover the Ethernet Statistics counters defined in RFC
1757. In addition to the counters defined in the Ethernet Statistics group, a counter is
included to count truncated frames as the FEC only supports frame lengths up to 2047
bytes. The RMON counters are implemented independently for transmit and receive to
insure accurate network statistics when operating in full duplex mode.
IEEE counters are included which support the Mandatory and Recommended counter
packages defined in section 5 of ANSI/IEEE Std. 802.3 (1998 edition). The IEEE Basic
Package objects are supported by the FEC but do not require counters in the MIB block. In
addition, some of the recommended package objects which are supported do not require
MIB counters. Counters for transmit and receive full duplex flow control frames are
included as well.
MOTOROLA
Name
Width
RCR
32
TCR
32
PALR
32
PAUR
32
OPD
32
IAUR
32
IALR
32
GAUR
32
GALR
32
TFWR
32
FRBR
32
FRSR
32
ERDSR
32
ETDSR
32
EMRBR
32
Chapter 17. Fast Ethernet Controller (FEC)
Description
Receive Control Register
Transmit Control Register
Physical Address Low Register
Physical Address High+ Type Field
Opcode + Pause Duration
Upper 32 bits of Individual Hash Table
Lower 32 Bits of Individual Hash Table
Upper 32 bits of Group Hash Table
Lower 32 bits of Group Hash Table
Transmit FIFO Watermark
FIFO Receive Bound Register
FIFO Receive FIFO Start Registers
Pointer to Receive Descriptor Ring
Pointer to Transmit Descriptor Ring
Maximum Receive Buffer Size
Programming Model
17-21
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