Interrupt Sources; Qadc Status Flags And Interrupt Sources - Motorola ColdFire MCF5281 User Manual

Interrupts
Table 27-26. QADC Status Flags and Interrupt Sources
Queue
Queue 1 Result written for last CCW in queue 1
Result written for a CCW with pause bit set in queue 1
Queue 2 Result written for last CCW in queue 2
Result written for a CCW with pause bit set in queue 2
If interrupts are enabled for an event, the QADC requests interrupt service when the event
occurs. Using interrupts does not require continuously polling the status flags to see if an
event has taken place; however, status flags must be cleared after an interrupt is serviced,
in order to remove the interrupt request
In both polled and interrupt-driven operating modes, status flags must be re-enabled after
an event occurs. Flags are re-enabled by clearing the appropriate QASR0 bits in a particular
sequence. QASR0 must first be read, then 0s must be written to the flags that are to be
cleared. If a new event occurs between the time that the register is read and the time that it
is written, the associated flag is not cleared.

27.10.2 Interrupt Sources

The QADC includes four sources of interrupt requests, each of which is separately enabled.
Each time the result is written for the last conversion command word (CCW) in a queue,
the completion flag for the corresponding queue is set, and when enabled, an interrupt is
requested. In the same way, each time the result is written for a CCW with the pause bit set,
the queue pause flag is set, and when enabled, an interrupt is requested. Refer to
Table 27-26.
The pause and complete interrupts for queue 1 and queue 2 have separate interrupt vector
levels, so that each source can be separately serviced.
27-76
Queue Activity
MCF5282 User's Manual
Status Interrupt
Flag Enable Bit
CF1 CIE1
PF1 PIE1
CF2 CIE2
PF2 PIE2
MOTOROLA