Concurrent Resets - Motorola ColdFire MCF5281 User Manual

Functional Description
28.5.2.1 Synchronous Reset Requests
In this discussion, the reference in parentheses refer to the state numbers in Figure 28-4. All
cycle counts given are approximate.
If the external RSTI signal is asserted by an external device for at least four rising
CLKOUT edges (3), if the watchdog timer times out, or if software requests a reset, the
reset control logic latches the reset request internally and enables the bus monitor (5). When
the current bus cycle is completed (6), RSTO is asserted (7). The reset control logic waits
until the RSTI signal is negated (8) and for the PLL to attain lock (9, 9A) before waiting
512 CLKOUT cycles (1). The reset control logic may latch the configuration according to
the RCON signal level (11, 11A) before negating RSTO (12).
If the external RSTI signal is asserted by an external device for at least four rising
CLKOUT edges during the 512 count (10) or during the wait for PLL lock (9A), the reset
flow switches to (8) and waits for the RSTI signal to be negated before continuing.
28.5.2.2 Internal Reset Request
If reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss
of lock (2), the reset control logic asserts RSTO (4). The reset control logic waits for the
PLL to attain lock (9, 9A) before waiting 512 CLKOUT cycles (1). Then the reset control
logic may latch the configuration according to the RCON pin level (11, 11A) before
negating RSTO (12).
If loss of lock occurs during the 512 count (10), the reset flow switches to (9A) and waits
for the PLL to lock before continuing.
28.5.2.3 Power-On Reset/Low-Voltage Detect Reset
When the reset sequence is initiated by power-on reset (0), the same reset sequence is
followed as for the other asynchronous reset sources.

28.5.3 Concurrent Resets

This section describes the concurrent resets. As in the previous discussion references in
parentheses refer to the state numbers in Figure 28-4.
28.5.3.1 Reset Flow
If a power-on reset or low-voltage detect condition is detected during any reset sequence,
the reset sequence starts immediately (0).
If the external RSTI pin is asserted for at least four rising CLKOUT edges while waiting
for PLL lock or the 512 cycles, the external reset is recognized. Reset processing switches
to wait for the external RSTI pin to negate (8).
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