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Initialization/Application Information
contents of the user's secured code stored in flash gets erased before security is disabled on
the MCU on the next reset or power-up sequence.
The LOCKOUT_RECOVERY instruction selects a 7-bit shift register for connection as a
shift path between the TDI pin and the TDO pin. When the user transitions the TAP
controller to the UPDATE-DR state, the 7-bit shift register is loaded into the 7-bit
JTAG_TFM_CLKDIV register and this value is output to the TFM's clock divider circuit.
When the user transitions the TAP controller to the RUN-TEST/IDLE state, the erase signal
to the TFM asserts and the lockout sequence starts. The controller must remain in that state
until the erase sequence has completed. Once the lockout recovery sequence has completed,
the user must reset both the JTAG TAP controller and the MCU to return to normal
operation.
31.5.3.8 CLAMP Instruction
The CLAMP instruction selects the bypass register and asserts internal reset while
simultaneously forcing all output pins and bidirectional pins configured as outputs to the
fixed values that are preloaded and held in the boundary scan update register. CLAMP
enhances test efficiency by reducing the overall shift path to a single bit (the bypass
register) while conducting an EXTEST type of instruction through the boundary scan
register.
31.5.3.9 BYPASS Instruction
The BYPASS instruction selects the bypass register, creating a single-bit shift register path
from the TDI pin to the TDO pin. BYPASS enhances test efficiency by reducing the overall
shift path when a device other than the ColdFire processor is the device under test on a
board design with multiple chips on the overall boundary scan chain. The shift register LSB
is forced to logic 0 on the rising edge of TCLK after entry into the capture-DR state.
Therefore, the first bit shifted out after selecting the bypass register is always logic 0. This
differentiates parts that support an IDCODE register from parts that support only the bypass
register.
31.6 Initialization/Application Information
31.6.1 Restrictions
The test logic is a static logic design, and TCLK can be stopped in either a high or low state
without loss of data. However, the system clock is not synchronized to TCLK internally.
Any mixed operation using both the test logic and the system functional logic requires
external synchronization.
MOTOROLA
Chapter 31. IEEE 1149.1 Test Access Port (JTAG)
31-11
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